1. Field of the Invention
This invention relates to a semiconductor memory apparatus, particularly to a semiconductor memory apparatus which is composed of memory cell array and has signal lines, that is, memory cell select lines (bit lines, word lines) selecting the memory cell for writing in and reading out data, and further relates to a testing apparatus for detecting whether there is a short circuit or not between the memory cell select lines (bit lines and/or word lines) thereof and to a method for relieving the semiconductor memory apparatus from short circuit caused by foreign matter between the memory cell select liens.
2. Description of Related Art
FIG. 1 is a schematic diagram showing a configuration example of a conventional- semiconductor memory apparatus.
In FIG. 1, reference symbol 1 designates a bit line, 2 a selector, 3 a row decoder, and 4 a memory cell array respectively.
The memory cell array 4 is configured by arranging memory cells in the form of matrix. The bit lines 1 as column direction memory cell select lines of the memory cell array 4 are provided in plural number and wired in parallel to each other, and each bit line 1 connects memory cells of each column on the memory cell array 4 to the selector 2. Further, the word lines (not shown) as row direction memory cell select lines are also provided in plural number and wired in parallel to each other, and each word line connects memory cells of each row on the memory cell array 4 to the row decoder 3.
Such a conventional semiconductor memory apparatus is operated as follows.
Assuming that one word line is designated by the row decoder 3, memory contents of all the memory cells on the designated world line are read out and outputted to all the bit lines 1, and only the data outputted to one or more bit lines 1 selected by the selector 2 are read out.
By the way, as shown in FIG. 1, when foreign matter E attaches to two bit lines 1, 1 each being adjacent to each other, inter bit line short circuit between bit lines is generated. This is also the same as the word lines.
Conventionally, rejection of products in which inter bit line and/or inter word line short circuit in the process of producing and examination has been performed by such an indirect method that the memory contents of the memory cells are read out and judged whether or not it coincides with a predetermined expected value, not such a method that whether or not inter bit line and/or inter word line is generated in real is examined directly.
As aforementioned, in the conventional semiconductor memory apparatus, since short circuit generated between the bit lines and/or inter word lines as memory cell select lines of the memory cells was judged by the indirect method, the apparatus was not reliable in accuracy. There was also a problem that it required a long time to examine short circuit.
Further, there is also a problem that yield is low in production process since a product which was judged to have generated inter bit line and/or inter word line short circuit was rejected as a defective.